Planar MOSFET — Device Physics Explorer — ICD, University of Twente

Device

n-channel p-channel

Channel length L

Channel width W

Oxide thickness t_ox

Body doping N_A

V_T adjust implant

Bias

V_GS

V_DS

V_SB (body bias)

Temperature T

Physics switches

Velocity saturation (carriers cannot exceed v_sat; makes I_D linear rather than quadratic in short devices) Vertical-field mobility degradation μ_eff = μ₀/(1+θV_ov′), zero below threshold Channel-length modulation (finite output resistance) Drain-induced barrier lowering: V_T falls with V_DS Source/drain series resistance

R_S = R_D (per µm of W)

Gate tunnelling leakage through the oxide Poly-silicon gate depletion

θ (mobility degradation)

Interface trap density D_it

Presets

Operating point

Output characteristics I_D(V_DS)

show the r_o tangent at this V_DS overlay the ideal square law (no v_sat, no CLM)

Where the saturation comes from

Transfer characteristic and transconductance

compare three V_DS values plot √I_D as well (V_T extraction)

I_D g_m √I_D other V_DS

Subthreshold region — the switch that never fully turns off

Leakage budget and V_T definitions

g_m/I_D versus inversion level — the analogue design map

Intrinsic gain and transit frequency

Cross-section: depletion, inversion and pinch-off

inversion charge depletion region lateral field pinch-off point

Along the channel: charge, field and carrier velocity

MOS capacitor: surface potential and charge

C–V curve

high frequency low frequency (quasi-static) C_ox

Band diagram through the gate stack

E_C, E_V E_F E_i (intrinsic level)

Short-channel effects versus gate length

What scaling costs: oxide field, leakage and gate tunnelling

What this model is, and where it stops. The channel current is the charge-based (EKV/ACM) form, which is one expression valid from weak through strong inversion — there is no patching of a subthreshold exponential onto a square law. Saturation is handled by an effective drain voltage V_DS,eff that smoothly limits at V_DSsat, so all V_DS dependence beyond pinch-off comes from channel-length modulation and DIBL, as it should. Poly depletion and the source/drain series resistance are solved self-consistently rather than subtracted.

Not included: quantum-mechanical inversion-layer thickness and the resulting C_ox degradation, gate current in the channel equation, self-heating, halo/pocket doping profiles, stress engineering, trap-assisted noise, and any 2-D solution of Poisson's equation — the short-channel terms here are the usual charge-sharing and scale-length fits. At extreme corners (a 25 nm channel with a 10 nm oxide, say, where V_T has gone negative) the lumped series resistance can make 2R_Sg_ds > 1 and I_D(V_GS) then dips by a few tenths of a percent; that is the lumped-element idealisation talking, not the transistor.